1. Field of the Invention The present invention relates to a display device.
2. Description of Related Art
In recent years, as disclosed in Japanese Unexamined Patent Application Publication Nos. 2006-079104 and 2008-070763, the development of the technique called double scanline style is progressing. In a liquid crystal display of the double scanline style, one video signal line is placed per two adjacent pixels for a plurality of pixels arranged in a row in an extended direction of a scan signal line. Then, two scan signal lines are respectively placed to sandwich the pixels arranged in a row. Thus, the number of video signal lines per pixel can be reduced by half. Additionally, it is possible to reduce the number of parts such as a video signal IC that drives the video signal lines, and thereby reducing the cost of the liquid crystal display.
A liquid crystal display of the double scanline style disclosed in Japanese Unexamined Patent Application Publication No. 2008-070763 is explained with reference to FIG. 9. FIG. 9 is a schematic circuit diagram showing a circuit configuration of the liquid crystal display disclosed in Japanese Unexamined Patent Application Publication No. 2008-070763. In FIG. 9, only the necessary parts of FIG. 9A of Japanese Unexamined Patent Application Publication No. 2008-070763 are illustrated.
As shown in FIG. 9, pixels 13, in which the gate of TFTs 10 are connected to first scan signal lines 11, and pixels 13, in which the gate of the TFT 10s are connected to second scan signal lines 12, are alternately arranged along the x-axis direction. In other words, the position of the TFT 10 in the pixel 13 varies from column to column. This applies to the liquid crystal display of the double scanline style disclosed in Japanese Unexamined Patent Application Publication No. 2006-079104.